This discussion examines artificial intelligence, AI, driven automation for semiconductor design and verification. William Wang of ChipAgents is founder and chief executive officer. Wang brings an artificial intelligence research background and holds a Doctor of Philosophy from Carnegie Mellon; they have held a professorship at the University of California Santa Barbara. In conversation with Gemma Allen of theCUBE for theCUBE + NYSE Wired: AI Factories at the New York Stock Exchange, the discussion explores an agentic AI platform, electronic design automation, EDA, digital verification and analog and mixed-signal design, and strategies to accelerate tape-out cycles.
Key takeaways include accelerated verification and end-to-end integrated circuit optimization. Wang reports that they reduce typical tape-out timelines from roughly 18 to 12 months for some customers. They emphasize intellectual property protection and data security and state that customer data are not used to train models. Wang describes an on-prem ontology layer for test-time exploration that enables secure model inference and iterative verification. Analysts observe a broader shift toward AI-native design and identify a large total addressable market across hyperscalers GPUs memory and robotics. The conversation highlights implications for EDA workflows semiconductor manufacturers and hardware developers.
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William Wang, ChipAgents
This discussion examines artificial intelligence, AI, driven automation for semiconductor design and verification. William Wang of ChipAgents is founder and chief executive officer. Wang brings an artificial intelligence research background and holds a Doctor of Philosophy from Carnegie Mellon; they have held a professorship at the University of California Santa Barbara. In conversation with Gemma Allen of theCUBE for theCUBE + NYSE Wired: AI Factories at the New York Stock Exchange, the discussion explores an agentic AI platform, electronic design automation, EDA, digital verification and analog and mixed-signal design, and strategies to accelerate tape-out cycles.
Key takeaways include accelerated verification and end-to-end integrated circuit optimization. Wang reports that they reduce typical tape-out timelines from roughly 18 to 12 months for some customers. They emphasize intellectual property protection and data security and state that customer data are not used to train models. Wang describes an on-prem ontology layer for test-time exploration that enables secure model inference and iterative verification. Analysts observe a broader shift toward AI-native design and identify a large total addressable market across hyperscalers GPUs memory and robotics. The conversation highlights implications for EDA workflows semiconductor manufacturers and hardware developers.
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play_circle_outlineAI-Driven Design Cuts Tape-Out to 12 Months, Expands from Verification to Architecture/Firmware/Analog for 200+ Semiconductor Customers
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play_circle_outlineAccelerating Tape-Out: Verification Bottlenecks and IC-Star Optimization for Performance, Power, Timing, and Area
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play_circle_outlineAgentic AI Scales Chip Design as Non-Traditional Companies Enter the ASIC Market